Aspects of semiconductor technology have focused on fabricating semiconductor devices having high integration and high performance. Production of highly integrated semiconductor devices may result in a reduction in the gate length of a MOS transistor, and the source/drain region thereof.
A semiconductor device having high integration may include a gate electrode, an interlayer dielectric layer, a contact electrode, and a multi-layer wiring that are vertically stacked on and/or over a semiconductor substrate. A chemical mechanical polishing (CMP) process may then be performed on the structure.
As illustrated in example FIG. 1, a method for manufacturing the MOS transistor may include performing a shallow trench isolation (STI) process on silicon semiconductor substrate 10 to form device isolating layer 12. A well-region may be formed by ion-implanting a low concentration impurity dopant such as a p-type impurity dopant into substrate 10 where device isolating layer 12 is formed.
An impurity dopant such as an n-type impurity dopant can then be ion-implanted into the well-region of semiconductor substrate 10 to form a threshold voltage control region.
Gate insulating layer 14, which may be composed of silicon oxide film (SiO2) may be thinly deposited on and/or over the overall surface of semiconductor substrate 10. Next, a doped polysilicon, as a gate conductive layer having a predetermined thickness, may then be deposited on and/or over gate insulating layer 14. The gate conductive layer may then be patterned using a dry etching process, using a gate mask, to form gate electrode 16. At this time, gate insulating layer 14 may also be patterned.
A low concentration impurity dopant such as an n-type impurity dopant may then be ion-implanted to form a LDD region. An insulating layer composed of a silicon nitride film (SiN) may then be deposited on and/or over the overall surface of structure. The insulating layer may then be etched using an etching process such as an etch back to form a pair of spacers 18 on the side walls of gate insulating layer 14 and gate electrode 16.
A high concentration impurity dopant such as an n-type impurity dopant may then be ion-implanted using gate electrode 16 and spacer 18 as masks to form source/drain region 20 in semiconductor substrate 10.
Thereafter, a metal layer such as titanium (Ti) for silicide, may then be deposited on and/or over the overall surface of the structure and an annealing process may be performed thereon to form titanium silicide (TiSi) film 22 on and/or over the uppermost surface of gate electrode 16 and the uppermost surface of source/drain region 20.
Interlayer dielectric layer 24 composed of a dielectric material such as phosphor-silicate glass (PSG), boro-silicate glass (BSG), boro-phospho silicate glass (BPSG) or undoped silicate glass (USG) may be deposited on and/or over the overall surface of semiconductor substrate 10 and the surface of interlayer dielectric layer 24 may be planarized using a chemical mechanical polishing (CMP) process.
Thereafter, a contact hole etching process may be performed on interlayer dielectric layer 24 to form a contact hole exposing the uppermost surface of silicide film 22 of gate electrode 16 or the uppermost surface of silicide film 22 of source/drain region 20. A conductive layer composed of a metal such as tungsten (W) may then be gap-filled in the contact hole and planarized using a chemical mechanical polishing (CMP) process to form a contact electrode.
Such a vertical MOS transistor requires use of a chemical mechanical polishing (CMP) process for planarizing the surface of the structure in order to remove the step of the surface of the structure. Furthermore, since the gap between gate electrodes or the contacts has been gradually reduced due to obtain a highly integrated semiconductor device, a bridge may be formed between devices having a fine gap thereby. Therefore, there have been problems that the electrical characteristics and the yield of the semiconductor device may become deteriorated.